A First-Order Logic Based Framework for Verifying Simulations

Modern science relies on simulation techniques for understanding phenomenon, exploring design options, or evaluating models. Assuring the correctness of simulators is a key problem where a multitude of solutions ranging from manual inspection to formal verification are applicable. Formal verification incorporates the rigor necessary but not all simulators are generated from formal specifications. Manual inspection is readily available but lacks the rigor and is prone to errors. In this paper, we describe an automated verification system (AVS) where the contraints that the system must adhere to are specified by the user in general purpose first-order logic. AVS translates these constraints into a verification program that scans the simulator trace and verifies that no constraints are violated. The advantage is the ability to verify any simulator trace using a formal specification of domain facts. Computer microarchitecture simulations were used to demonstrate the proposed approach. The system was implemented successfully to yield preliminary results.